High Level Synthesis of Asics Under Timing and Synchronization Constraints by David C. Ku, Giovanni Demicheli

High Level Synthesis of Asics Under Timing and Synchronization Constraints

The Springer International Engineering and Computer Science

David C. Ku, Giovanni Demicheli

294 pages • missing pub info (editions)

nonfiction art computer science design technology informative medium-paced
Powered by AI (Beta)
Loading...

Description

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints a...

Read more

Community Reviews

Loading...

Content Warnings

Loading...